Datasheet

Section 7 DMA Controller (DMAC)
Rev.7.00 Mar. 18, 2009 page 317 of 1136
REJ09B0109-0700
IOAR. The transfer direction can be specified by the DTDIR bit in DMACR. Table 7.7
summarizes register functions in repeat mode.
Table 7.7 Register Functions in Repeat Mode
Function
Register DTDIR = 0 DTDIR = 1 Initial Setting Operation
23 0
MAR
Source
address
register
Destination
address
register
Start address of
transfer destination
or transfer source
Incremented/
decremented every
transfer.
Initial setting is
restored when value
reaches H'0000
23 15 0
IOARH'FF
Destination
address
register
Source
address
register
Start address of
transfer source or
transfer destination
Fixed
0
ETCRH
7
0
ETCRL
7
Holds number of
transfers
Transfer counter
Number of transfers
Number of transfers
Fixed
Decremented every
transfer.
Loaded with ETCRH
value when count
reaches H'00
MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is
incremented or decremented by 1 or 2 each time a byte or word is transferred. IOAR specifies the
lower 16 bits of the other address. The upper 8 bits of IOAR have a value of H'FF. The number of
transfers is specified as 8 bits by ETCRH and ETCRL. The maximum number of transfers, when
H'00 is set in both ETCRH and ETCRL, is 256.
In repeat mode, ETCRL functions as the transfer counter, and ETCRH is used to hold the number
of transfers. ETCRL is decremented by 1 each time a data transfer is executed, and when its value
reaches H'00, it is loaded with the value in ETCRH. At the same time, the value set in MAR is
restored in accordance with the values of the DTSZ and DTID bits in DMACR. The MAR
restoration operation is as shown below.
MAR = MAR – (–1)
DTID
· 2
DTSZ
· ETCRH
The same value should be set in ETCRH and ETCRL.