Datasheet

Section 7 DMA Controller (DMAC)
Rev.7.00 Mar. 18, 2009 page 342 of 1136
REJ09B0109-0700
Single Address Mode (Write): Figure 7.28 shows a transfer example in which TEND output is
enabled and byte-size single address mode transfer (write) is performed from an external device to
external 8-bit, 2-state access space.
DMA write
A
ddress bus
φ
DMA
dead
HWR
DACK
TEND
Bus
release
LWR
DMA write DMA write DMA write
Bus
release
Bus
release
Bus
release
Bus
release
Last transfer
cycle
Figure 7.28 Example of Single Address Mode Transfer (Byte Write)
Figure 7.29 shows a transfer example in which TEND output is enabled and word-size single
address mode transfer (write) is performed from an external device to external 8-bit, 2-state access
space.