Datasheet

Section 8 EXDMA Controller (EXDMAC)
Rev.7.00 Mar. 18, 2009 page 360 of 1136
REJ09B0109-0700
Figure 8.1 shows a block diagram of the EXDMAC.
Bus controller
Internal data bus
Interrupt request
signals to CPU
for individual
channels
External pins
EDMDR
EDACR
EDTCR
EDDAR
EDSAR
Processor
Address buffer
Data buffer
Control logic
Module data bus
EDREQ
EDRAK
ETEND
EDACK
Legend:
EDSAR: EXDMA source address register
EDDAR: EXDMA destination address register
EDTCR: EXDMA transfer count register
EDMDR: EXDMA mode control register
EDACR: EXDMA address control register
Figure 8.1 Block Diagram of EXDMAC