Datasheet

Rev.7.00 Mar. 18, 2009 page xliv of lxvi
REJ09B0109-0700
Figure 3.9 Memory Map for H8S/2373 and H8S/2373R............................................................ 86
Figure 3.10 Memory Map for H8S/2372 and H8S/2372R (1)...................................................... 87
Figure 3.11 Memory Map for H8S/2372 and H8S/2372R (2)...................................................... 88
Figure 3.12 Memory Map for H8S/2371 and H8S/2371R (1)...................................................... 89
Figure 3.13 Memory Map for H8S/2371 and H8S/2371R (2)...................................................... 90
Figure 3.14 Memory Map for H8S/2370 and H8S/2370R (1)...................................................... 91
Figure 3.15 Memory Map for H8S/2370 and H8S/2370R (2)...................................................... 92
Section 4 Exception Handling............................................................................. 93
Figure 4.1 Reset Sequence (Advanced Mode with On-chip ROM Enabled).............................. 96
Figure 4.2 Reset Sequence (Advanced Mode with On-chip ROM Disabled) ............................ 97
Figure 4.3 Stack Status after Exception Handling.................................................................... 100
Figure 4.4 Operation when SP Value Is Odd............................................................................ 101
Section 5 Interrupt Controller............................................................................ 103
Figure 5.1 Block Diagram of Interrupt Controller.................................................................... 104
Figure 5.2 Block Diagram of Interrupts IRQ15 to IRQ0.......................................................... 121
Figure 5.3 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0. 128
Figure 5.4 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 2. 130
Figure 5.5 Interrupt Exception Handling.................................................................................. 131
Figure 5.6 Conflict between Interrupt Generation and Disabling............................................. 134
Section 6 Bus Controller (BSC) ........................................................................ 137
Figure 6.1 Block Diagram of Bus Controller............................................................................ 138
Figure 6.2 Read Strobe Negation Timing (Example of 3-State Access Space)........................ 150
Figure 6.3 CS and Address Assertion Period Extension
(Example of 3-State Access Space and RDNn = 0) ................................................ 152
Figure 6.4 RAS Signal Assertion Timing (2-State Column Address Output Cycle,
Full Access)............................................................................................................. 163
Figure 6.5 CAS Latency Control Cycle Disable Timing during Continuous Synchronous
DRAM Space Write Access (for CAS Latency 2) .................................................. 166
Figure 6.6 Area Divisions......................................................................................................... 171
Figure 6.7 CSn Signal Output Timing (n = 0 to 7)................................................................... 176
Figure 6.8 Access Sizes and Data Alignment Control (8-Bit Access Space) ........................... 177
Figure 6.9 Access Sizes and Data Alignment Control (16-Bit Access Space) ......................... 177
Figure 6.10 Bus Timing for 8-Bit, 2-State Access Space........................................................... 179
Figure 6.11 Bus Timing for 8-Bit, 3-State Access Space........................................................... 180
Figure 6.12 Bus Timing for 16-Bit, 2-State Access Space (Even Address Byte Access)........... 181
Figure 6.13 Bus Timing for 16-Bit, 2-State Access Space (Odd Address Byte Access)............ 182
Figure 6.14 Bus Timing for 16-Bit, 2-State Access Space (Word Access) ................................ 183
Figure 6.15 Bus Timing for 16-Bit, 3-State Access Space (Even Address Byte Access)........... 184