Datasheet

Section 8 EXDMA Controller (EXDMAC)
Rev.7.00 Mar. 18, 2009 page 400 of 1136
REJ09B0109-0700
8.4.10 EXDMAC Bus Cycles (Single Address Mode)
Single Address Mode (Read): Figure 8.22 shows an example of transfer when ETEND output is
enabled, and byte-size, single address mode transfer (read) is performed from external 8-bit, 2-
state access space to an external device.
RD
ETEND
A
ddress bus
φ
Bus release Bus release Bus releaseLast
transfer
cycle
DMA read
EDACK
DMA readDMA readDMA read
Bus releaseBus release
Figure 8.22 Example of Single Address Mode (Byte Read) Transfer
Figure 8.23 shows an example of transfer when ETEND output is enabled, and word-size, single
address mode transfer (read) is performed from external 8-bit, 2-state access space to an external
device.
DMA read
RD
ETEND
A
ddress bus
φ
Bus release Bus release Bus
releas
e
Last transfer cycle
EDACK
Bus release
DMA readDMA read
Figure 8.23 Example of Single Address Mode (Word Read) Transfer