Datasheet

Section 8 EXDMA Controller (EXDMAC)
Rev.7.00 Mar. 18, 2009 page 410 of 1136
REJ09B0109-0700
φ pin
EDREQ
EDACK
ETEND
EDRAK
Bus cycle
CPU
operation
Last transfer cycle2 bus cycles
CPU cycle
External
space
External
space
External
space
External
space
External
space
External
space
EXDMA single
transfer cycle
EXDMA single
transfer cycle
CPU cycle CPU cycle CPU cycle CPU cycle CPU cycle
Figure 8.36 External Request/Cycle Steal Mode/Normal Transfer Mode
(CPU Cycles/Single Address Mode/Low Level Sensing)
φ pin
EDREQ
EDACK
EDRAK
Bus cycle
EDREQ
acceptance
internal
processing
state
Bus release Bus release Bus release
Start of high
level sensing
Start of high
level sensing
Start of high
level sensing
EXDMA single
transfer cycle
EXDMA single
transfer cycle
EXDMA single
transfer cycle
Edge confirmation
Start of transfer
processing
Edge confirmation
Start of transfer
processing
Edge confirmation
Start of transfer
processing
Figure 8.37 External Request/Cycle Steal Mode/Normal Transfer Mode
(No Contention/Single Address Mode/Falling Edge Sensing)