Datasheet

Rev.7.00 Mar. 18, 2009 page l of lxvi
REJ09B0109-0700
Figure 8.40 External Request/Cycle Steal Mode/Block Transfer Mode
(No Contention/Single Address Mode/Falling Edge Sensing/BGUP = 0).............. 413
Figure 8.41 External Request/Cycle Steal Mode/Block Transfer Mode
(CPU Cycles/Single Address Mode/Low Level Sensing/BGUP = 0) ..................... 414
Figure 8.42 External Request/Cycle Steal Mode/Block Transfer Mode
(CPU Cycles/Dual Address Mode/Low Level Sensing/BGUP = 1)........................ 415
Figure 8.43 External Request/Cycle Steal Mode/Block Transfer Mode
(CPU Cycles/Single Address Mode/Low Level Sensing/BGUP = 1) ..................... 416
Figure 8.44 External Request/Cycle Steal Mode/Block Transfer Mode
(Contention with Another Channel/Dual Address Mode/Low Level Sensing)....... 417
Figure 8.45 Transfer End Interrupt Logic................................................................................... 420
Figure 8.46 Example of Procedure for Restarting Transfer on Channel
in which Transfer End Interrupt Occurred .............................................................. 421
Section 9 Data Transfer Controller (DTC)........................................................ 425
Figure 9.1 Block Diagram of DTC........................................................................................... 426
Figure 9.2 Block Diagram of DTC Activation Source Control ................................................ 433
Figure 9.3 Correspondence between DTC Vector Address and Register Information............. 434
Figure 9.4 Correspondence between DTC Vector Address and Register Information............. 434
Figure 9.5 Flowchart of DTC Operation .................................................................................. 438
Figure 9.6 Memory Mapping in Normal Mode ........................................................................ 440
Figure 9.7 Memory Mapping in Repeat Mode ......................................................................... 441
Figure 9.8 Memory Mapping in Block Transfer Mode ............................................................ 442
Figure 9.9 Operation of Chain Transfer.................................................................................... 443
Figure 9.10 DTC Operation Timing (Example in Normal Mode or Repeat Mode) ................... 444
Figure 9.11 DTC Operation Timing (Example of Block Transfer Mode,
with Block Size of 2)............................................................................................... 445
Figure 9.12 DTC Operation Timing (Example of Chain Transfer) ............................................ 445
Figure 9.13 Chain Transfer when Counter = 0 ........................................................................... 451
Section 11 16-Bit Timer Pulse Unit (TPU) .......................................................545
Figure 11.1 Block Diagram of TPU............................................................................................ 548
Figure 11.2 Example of Counter Operation Setting Procedure .................................................. 583
Figure 11.3 Free-Running Counter Operation............................................................................ 584
Figure 11.4 Periodic Counter Operation..................................................................................... 585
Figure 11.5 Example of Setting Procedure for Waveform Output by Compare Match.............. 586
Figure 11.6 Example of 0 Output/1 Output Operation ............................................................... 587
Figure 11.7 Example of Toggle Output Operation ..................................................................... 587
Figure 11.8 Example of Setting Procedure for Input Capture Operation.................................... 588
Figure 11.9 Example of Input Capture Operation ...................................................................... 589
Figure 11.10 Example of Synchronous Operation Setting Procedure .......................................... 590