Datasheet

Section 10 I/O Ports
Rev.7.00 Mar. 18, 2009 page 469 of 1136
REJ09B0109-0700
• P12/PO10/TIOCC0/TCLKA
The pin function is switched as shown below according to the combination of the TPU channel
0 settings (by bits MD3 to MD0 in TMDR_0, bits IOC3 to IOC0 in TIORL_0, and bits CCLR2
to CCLR0 in TCR_0), bits TPSC2 to TPSC0 in TCR_0 to TCR_5, bit NDER10 in NDERH,
and bit P12DDR.
TPU channel 0
settings
(1) in table
below
(2) in table below
P12DDR ⎯ 0 1 1
NDER10 ⎯ ⎯ 0 1
P12 input P12 output PO10 output Pin function TIOCC0 output
TIOCC0 input
*
1
TCLKA input
*
2
TPU channel 0
settings
(2) (1) (2) (1) (1) (2)
MD3 to MD0 B'0000 B'001× B'0010 B''0011
IOC3 to IOC0 B'0000
B'0100
B'1×××
B'0001 to
B'0011
B'0101 to
B'0111
B'××00 Other
than B'××00
Other than B'××00
CCLR2, CCLR0 ⎯ ⎯ ⎯ ⎯ Other
than
B'101
B'101
Output function ⎯ Output
compare
output
⎯ PWM
*
3
mode 1
output
PWM mode
2 output
⎯
Legend:
×: Don’t care
Notes: 1. TIOCC0 input when MD3 to MD0 = B'0000 and IOC3 to IOC0 = B'10××.
2. TCLKA input when the setting for any of TCR_0 to TCR_5 is TPSC2 to TPSC0 = B'100.
TCLKA input when phase counting mode is set for channels 1 and 5.
3. TIOCD0 output disabled.
Output disabled and settings (2) effective when BFA = 1 or BFB = 1 in TMDR_0.