Datasheet

Rev.7.00 Mar. 18, 2009 page lvii of lxvi
REJ09B0109-0700
Figure 26.22 Self-Refresh Timing (Return from Software Standby Mode: RAST = 1)............. 1083
Figure 26.23 External Bus Release Timing................................................................................ 1084
Figure 26.24 External Bus Request Output Timing.................................................................... 1084
Figure 26.25 Synchronous DRAM Basic Access Timing (CAS Latency 2) .............................. 1085
Figure 26.26 Synchronous DRAM Self-Refresh Timing ........................................................... 1086
Figure 26.27 Read Data: Two-State Expansion (CAS Latency 2).............................................. 1087
Figure 26.28 DMAC and EXDMAC Single Address Transfer Timing: Two-State Access....... 1088
Figure 26.29 DMAC and EXDMAC Single Address Transfer Timing: Three-State Access..... 1089
Figure 26.30 DMAC and EXDMAC TEND/ETEND Output Timing ....................................... 1090
Figure 26.31 DMAC and EXDMAC DREQ/EDREQ Input Timing.......................................... 1090
Figure 26.32 EXDMAC EDRAK Output Timing...................................................................... 1090
Figure 26.33 I/O Port Input/Output Timing................................................................................ 1091
Figure 26.34 PPG Output Timing............................................................................................... 1091
Figure 26.35 TPU Input/Output Timing..................................................................................... 1091
Figure 26.36 TPU Clock Input Timing....................................................................................... 1092
Figure 26.37 8-Bit Timer Output Timing ................................................................................... 1092
Figure 26.38 8-Bit Timer Clock Input Timing ........................................................................... 1092
Figure 26.39 8-Bit Timer Reset Input Timing............................................................................ 1092
Figure 26.40 WDT Output Timing............................................................................................. 1093
Figure 26.41 SCK Clock Input Timing ...................................................................................... 1093
Figure 26.42 SCI Input/Output Timing: Synchronous Mode ..................................................... 1093
Figure 26.43 A/D Converter External Trigger Input Timing...................................................... 1093
Figure 26.44 I
2
C Bus Interface 2 Input/Output Timing (Option) ............................................... 1094
Appendix ........................................................................................................1095
Figure C.1 Package Dimensions (FP-144H) ........................................................................... 1106
Figure C.2 Package Dimensions (TLP-145V)......................................................................... 1107
Figure D.1 Timing of Address Bus, RD, HWR, and LWR
(8-Bit Bus, 3-State Access, No Wait).................................................................... 1109