Datasheet

Section 10 I/O Ports
Rev.7.00 Mar. 18, 2009 page 529 of 1136
REJ09B0109-0700
10.14.1 Port F Data Direction Register (PFDDR)
The individual bits of PFDDR specify input or output for the pins of port F.
PFDDR cannot be read; if it is, an undefined value will be read.
Bit Bit Name Initial Value R/W Description
7 PF7DDR 1/0
*
W
6 PF6DDR 0 W
5 PF5DDR 0 W
4 PF4DDR 0 W
3 PF3DDR 0 W
2 PF2DDR 0 W
1 PF1DDR 0 W
0 PF0DDR 0 W
• Modes 7 (when EXPE = 1), 1, 2, and 4
Pin PF7 functions as the φ output pin when the
corresponding PFDDR bit is set to 1, and as an
input port when the bit is cleared to 0.
Pin PF6 functions as the AS output pin when
A
SOE is set to 1. When ASOE is cleared to 0, pin
PF6 is an I/O port and its function can be
switched with PF6DDR.
Pins PF5 and PF4 are automatically designated
as bus control outputs (RD and HWR).
Pin PF3 functions as the LWR output pin when
LWROE is set to 1. When LWROE is cleared to
0, pin PF3 is an I/O port and its function can be
switched with PF3DDR.
Pins PF2 to PF0 function as bus control
input/output pins (LCAS, UCAS, and WAIT) when
the appropriate bus controller settings are made.
Otherwise, these pins are output ports when
PFDDR is set to 1 and are input ports when
PFDDR is cleared to 0.
• Mode 7 (when EXPE = 0)
Pin PF7 functions as the φ output pin when the
corresponding PFDDR bit is set to 1, and as an
input port when the bit is cleared to 0.
Pins PF6 to PF0 are I/O ports, and their functions
can be switched with PFDDR.
Note: * PF7DDR is initialized to 1 in modes 1, 2, and 4, and to 0 in mode 7.