Datasheet

Section 11 16-Bit Timer Pulse Unit (TPU)
Rev.7.00 Mar. 18, 2009 page 618 of 1136
REJ09B0109-0700
Status Flag Clearing Timing: After a status flag is read as 1 by the CPU, it is cleared by writing
0 to it. When the DTC or DMAC is activated, the flag is cleared automatically. Figure 11.42
shows the timing for status flag clearing by the CPU, and figure 11.43 shows the timing for status
flag clearing by the DTC or DMAC.
Status flag
Write signal
A
ddress
TSR address
Interrupt
request
signal
TSR write cycle
T
1
T
2
φ
Figure 11.42 Timing for Status Flag Clearing by CPU
Interrupt
request
signal
Status flag
A
ddress
Source address
DTC/DMAC
read cycle
T
1
T
2
Destination
address
T
1
T
2
DTC/DMAC
write cycle
φ
Figure 11.43 Timing for Status Flag Clearing by DTC/DMAC Activation