Datasheet

Section 11 16-Bit Timer Pulse Unit (TPU)
Rev.7.00 Mar. 18, 2009 page 625 of 1136
REJ09B0109-0700
11.10.9 Contention between TGR Write and Input Capture
If the input capture signal is generated in the T
2
state of a TGR write cycle, the input capture
operation takes precedence and the write to TGR is not performed.
Figure 11.50 shows the timing in this case.
Input capture
signal
Write signal
A
ddress
φ
TCNT
TGR write cycle
T
1
T
2
M
TGR
M
TGR address
Figure 11.50 Contention between TGR Write and Input Capture