Datasheet

Section 13 8-Bit Timers (TMR)
Rev.7.00 Mar. 18, 2009 page 671 of 1136
REJ09B0109-0700
13.8.2 Contention between TCNT Write and Increment
If a timer counter clock pulse is generated during the T
2
state of a TCNT write cycle, the write
takes priority and the counter is not incremented.
Figure 13.11 shows this operation.
A
ddress
φ
TCNT address
Internal write signal
TCNT input clock
TCNT
NM
T
1
T
2
TCNT write cycle by CPU
Counter write data
Figure 13.11 Contention between TCNT Write and Increment