Datasheet

Section 13 8-Bit Timers (TMR)
Rev.7.00 Mar. 18, 2009 page 672 of 1136
REJ09B0109-0700
13.8.3 Contention between TCOR Write and Compare Match
During the T
2
state of a TCOR write cycle, the TCOR write has priority and the compare match
signal is inhibited even if a compare match event occurs as shown in figure 13.12.
When using the TMR, ICR input capture is in contention with compare match in the same way as
writes to the TCOR. In such cases input capture has precedence and the compare match signal is
inhibited.
A
ddress
φ
TCOR address
Internal write signal
TCNT
TCOR
NM
T
1
T
2
TCOR write cycle by CPU
TCOR write data
N N + 1
Compare match signal
Inhibited
Figure 13.12 Contention between TCOR Write and Compare Match