Datasheet

Section 13 8-Bit Timers (TMR)
Rev.7.00 Mar. 18, 2009 page 675 of 1136
REJ09B0109-0700
No.
Timing of Switchover
by Means of CKS1
and CKS0 Bits
TCNT Clock Operation
4 Switching from high
to high
Clock before
switchover
Clock after
switchover
TCNT clock
TCNT
CKS bit write
N N + 1 N + 2
Notes: 1. Includes switching from low to stop, and from stop to low.
2. Includes switching from stop to high.
3. Includes switching from high to stop.
4. Generated on the assumption that the switchover is a falling edge; TCNT is
incremented.
13.8.6 Mode Setting with Cascaded Connection
If 16-bit counter mode and compare match count mode are specified at the same time, input clocks
for TCNT_0 and TCNT_1 are not generated, and the counter stops. Do not specify 16-bit counter
and compare match count modes simultaneously.
13.8.7 Interrupts in Module Stop Mode
If module stop mode is entered when an interrupt has been requested, it will not be possible to
clear the CPU interrupt source or the DTC and DMAC activation source. Interrupts should
therefore be disabled before entering module stop mode.