Datasheet

Rev.7.00 Mar. 18, 2009 page viii of lxvi
REJ09B0109-0700
Item Page Revision (See Manual for Details)
Section 8 EXDMA
Controller (EXDMAC)
359 Description amended
… The EXDMAC can carry out high-speed data transfer, in
place of the CPU, to and from external devices and external
memory with a DACK (DMA transfer notification) facility.
8.3.5 EXDMA
Address Control
Register (EDACR)
370 Table amended
Bit Bit Name Initial Value R/W Description
15
14
SAT1
SAT0
0
0
R/W
R/W
Source Address Update Mode
These bits specify incrementing/decrementing of
the transfer source address (EDSAR). When an
external device with DACK is designated as the
transfer source in single address mode, the
specification by these bits is ignored.
0×: Fixed
10: Incremented (+1 in byte transfer, +2 in word
transfer)
11: Decremented (–1 in byte transfer, –2 in word
transf
er)
372 Table amended
Bit Bit Name Initial Value R/W Description
7
6
DAT1
DAT0
0
0
R/W
R/W
Destination Address Update Mode
These bits specify incrementing/decrementing of
the transfer destination address (EDDAR). When
an external device with DACK is designated as the
transfer destination in single address mode, the
specification by these bits is ignored.
0×: Fixed
10: Incremented (+1 in byte transfer, +2 in word
transfer)
11: Decremented (–1 in byte transfer, –2 in word
transf
er)
8.4.2 Address Modes
Single Address Mode:
376 Description amended
… In the example of transfer between external memory and an
external device with DACK shown in figure 8.3, data is output to
the data bus by the external device and written to external
memory in the same bus cycle.
The transfer direction, that is whether the external device with
DACK is the transfer source or transfer destination, can be
specified with the SDIR bit in EDMDR. Transfer is performed
from the external memory (EDSAR) to the external device with
DACK when SDIR = 0, and from the external device with DACK
to the external memory (EDDAR) when SDIR = 1.