Datasheet

Section 22 Masked ROM
Rev.7.00 Mar. 18, 2009 page 953 of 1136
REJ09B0109-0700
Section 22 Masked ROM
The H8S/2375 and H8S/2375R have 256 kbytes of masked ROM. The on-chip ROM is connected
to the CPU, data transfer controller (DTC), and DMA controller (DMAC) with a 16-bit data bus.
The on-chip ROM can be accessed by the CPU, DTC, and DMAC in 8 or 16-bit units. The data in
the on-chip ROM can always be accessed in one state.
H'000000
H'000002
H'03FFFE
H'000001
H'000003
H'03FFFF
Internal data bus (upper 8 bits)
Internal data bus (lower 8 bits)
Figure 22.1 Block Diagram of 256-kbyte Masked ROM (HD6432375)
The on-chip ROM is enabled or disabled according to the operating mode. The operating mode is
selected by the mode setting pins MD2 to MD0 as shown in table 3.1. Select mode 4 or 7 when the
on-chip ROM is used, and mode 1 or 2 when the on-chip ROM is not used. The on-chip ROM is
allocated in area 0.