Datasheet

Section 24 Power-Down Modes
Rev.7.00 Mar. 18, 2009 page 972 of 1136
REJ09B0109-0700
• EXMSTPCRL
Bit Bit Name Initial Value R/W Module
7 MSTP23 1 R/W ⎯
6 MSTP22 1 R/W ⎯
5 MSTP21 1 R/W ⎯
4 MSTP20 1 R/W I
2
C bus interface 2_1 (IIC2_1)
3 MSTP19 1 R/W I
2
C bus interface 2_0 (IIC2_0)
2 MSTP18 1 R/W ⎯
1 MSTP17 0 R/W ⎯
0 MSTP16 1 R/W ⎯
24.2 Operation
24.2.1 Clock Division Mode
When bits SCK2 to SCK0 in SCKCR are set to a value from 001 to 101, a transition is made to
clock division mode at the end of the bus cycle. In clock division mode, the CPU, bus masters, and
on-chip peripheral functions all operate on the operating clock (1/2, 1/4) specified by bits SCK2 to
SCK0.
Clock division mode is cleared by clearing all of bits SCK2 to SCK0 to 0. A transition is made to
high-speed mode at the end of the bus cycle, and clock division mode is cleared.
If a SLEEP instruction is executed while the SSBY bit in SBYCR is cleared to 0, the chip enters
sleep mode. When sleep mode is cleared by an interrupt, clock division mode is restored.
If a SLEEP instruction is executed while the SSBY bit in SBYCR is set to 1, the chip enters
software standby mode. When software standby mode is cleared by an external interrupt, clock
division mode is restored.
When the RES pin is driven low, the reset state is entered and clock division mode is cleared. The
same applies to a reset caused by watchdog timer overflow.
When the STBY pin is driven low, a transition is made to hardware standby mode.