Datasheet

Rev.7.00 Mar. 18, 2009 page ix of lxvi
REJ09B0109-0700
Item Page Revision (See Manual for Details)
8.4.2 Address Modes
Figure 8.3 Data Flow in
Single Address Mode
377 Figure amended
External
memory
External device
with DACK
Figure 8.4 Example of
Timing in Single Address
Mode
378 Figure amended
EXDMA cycle
EDSAR
Address to external memory space
RD signal to external memory space
Data output from external memory
Address bus
φ
RD
WR
EDACK
ETEND
Data bus
EXDMA cycle
EDDAR
Address to external memory space
WR signal to external memory space
Address bus
φ
Transfer from external memory to external device with DACK
Transfer from external device with DACK to external memory
RD
WR
EDACK
ETEND
Data bus
Data output from external device
with DACK