Datasheet

Section 26 Electrical Characteristics
Rev.7.00 Mar. 18, 2009 page 1077 of 1136
REJ09B0109-0700
Tp
t
AD
t
AS3
t
AH1
t
CSD2
t
PCH2
t
AS2
t
AC1
t
OED1
t
OED1
t
AA3
t
AC4
t
WCS1
t
WCH1
t
WRD2
t
WDD
t
WDS1
t
WDH2
t
RDS2
t
RDH2
t
AH2
t
CSD3
t
CASD1
t
CASD1
t
CASW1
t
AD
φ
A23 to A0
RAS5 to RAS2
UCAS
LCAS
OE, RD
HWR
D15 to D0
OE, RD
HWR
D15 to D0
AS
Tr Tc1
Tc2
Read
Write
DACK0, DACK1
EDACK2, EDACK3
t
DACD1
t
DACD2
t
EDACD1
t
EDACD2
Note:
DACK and EDACK timing: when DDS = 0 and EDDS = 0
RAS timing: when RAST = 0
t
WRD2
Figure 26.14 DRAM Access Timing: Two-State Access