Datasheet

Section 26 Electrical Characteristics
Rev.7.00 Mar. 18, 2009 page 1078 of 1136
REJ09B0109-0700
Tp Tr Tc1 Tcw Tcwp Tc2
φ
A23 to A0
RAS5 to RAS2
UCAS, LCAS
OE, RD
HWR
D15 to D0
UCAS, LCAS
OE, RD
HWR
t
WTS
t
WTH
t
WTS
t
WTH
D15 to D0
WAIT
AS
Read
Write
Tcw : Wait cycle inserted by programmable wait function
Tcwp: Wait cycle inserted by pin wait function
DACK0, DACK1
EDACK2, EDACK3
DACK and EDACK timing: when DDS = 0 and EDDS = 0
RAS timing: when RAST = 0
Note:
Figure 26.15 DRAM Access Timing: Two-State Access, One Wait