Datasheet

Section 26 Electrical Characteristics
Rev.7.00 Mar. 18, 2009 page 1089 of 1136
REJ09B0109-0700
T
1
t
DACD1
t
EDACD1
t
DACD2
t
EDACD2
φ
A
23 to A0
CS7 to CS0
AS
RD
(read)
D15 to D0
(read)
HWR, LWR
(write)
D15 to D0
(write)
DACK0, DACK1
EDACK2, EDACK3
T
2
T
3
Figure 26.29 DMAC and EXDMAC Single Address Transfer Timing: Three-State Access