Datasheet

Rev.7.00 Mar. 18, 2009 page xiii of lxvi
REJ09B0109-0700
Item Page Revision (See Manual for Details)
15.4.4 SCI
Initialization
(Asynchronous Mode)
727 Description added
Before transmitting and receiving data, you should first clear the
TE and RE bits in SCR to 0, then initialize the SCI as shown in
figure 15.5. Do not write to SMR, SCMR, IrCR, or SEMR while
the SCI is operating. This also applies to writing the same data
as the current register contents. …
15.6.2 SCI
Initialization (Clocked
Synchronous Mode)
741 Description added
Before transmitting and receiving data, you should first clear the
TE and RE bits in SCR to 0, then initialize the SCI as described
in a sample flowchart in figure 15.15. Do not write to SMR,
SCMR, IrCR, or SEMR while the SCI is operating. This also
applies to writing the same data as the current register contents.
…
Section 16 I
2
C Bus
Interface 2 (IIC2)
(Option)
771 Description amended
The I
2
C bus interface conforms to and provides a subset of the
NXP Semiconductors I
2
C bus (inter-IC bus) interface (Rev. 3)
standard and fast mode functions. The register configuration
that controls the I
2
C bus differs partly from the NXP
Semiconductors configuration, however.
16.3.1 I
2
C Bus Control
Register A (ICCRA)
Table 16.2 Transfer
Rate
776 Table amended
Bit 3 Bit 2 Bit 1 Bit 0
Transfer Rate
CKS3 CKS2 CKS1 CKS0 Clock
φ
=
8 MHz
φ
=
10 MHz
φ
=
20 MHz
φ
=
25 MHz
φ
=
33 MHz
φ
=
34 MHz*
1
φ
=
35 MHz*
2
0 φ/28 286 kHz 357 kHz 714 kHz*
3
893 kHz*
3
1179 kHz*
3
1214 kHz*
3
1250 kHz*
3
0
1 φ/40 200 kHz 250 kHz 500 kHz*
3
625 kHz*
3
825 kHz*
3
850 kHz*
3
875 kHz*
3
0 φ/48 167 kHz 208 kHz 417 kHz*
3
521 kHz*
3
688 kHz*
3
708 kHz*
3
729 kHz*
3
0*
4
1
1 φ/64 125 kHz 156 kHz 313 kHz 391 kHz 516 kHz*
3
531 kHz*
3
547 kHz*
3
0*
4
Notes 3 and 4 added
3. I
2
C bus interface specification (standard mode: max. 100
kHz, fast mode: max. 400 kHz).
4. Due to load conditions, etc., it may not be possible to attain
the specified transfer rate when CKS3 and CKS2 are both
cleared to 0 (bit period: 7.5 tcyc) and the operating
frequency is 20 MHz or higher. Use a bit period other than
7.5 tcyc when the operating frequency exceeds 20 MHz.