Datasheet

Rev.7.00 Mar. 18, 2009 page xvii of lxvi
REJ09B0109-0700
Item Page Revision (See Manual for Details)
21.4.2 User Program
Mode
(2) Programming
Procedure in User
Program Mode
6. The FPEFEQ and
FUBRA parameters are
set for initialization.
889 Description amended
…For details on the frequency setting, see the description in
21.3.2 (2) (a), Flash programming/erasing frequency parameter
(FPEFEQ: general register ER0 of CPU).
…For details, see the descriptions in 21.3.2 (2) (a), Flash
programming/erasing frequency parameter (FPEFEQ: general
register ER0 of CPU), and 21.3.2 (2) (b), Flash user branch
address setting parameter (FUBRA: general register ER1 of
CPU).
21.8 Serial
Communication
Interface Specification
for Boot Mode
(4) Inquiry and
Selection States
(b) Device Selection
930 Description amended
• Size (one byte): Amount of device-code data
This is fixed at 4
Figure 21.21
Programming
Sequence
942 Figure amended
Transfer of the
programming
program
Host Boot program
Programming selection (H'42, H'43 )
(9) Programming/
Erasing State
(b) 128-byte
programming
943 Description amended
• Programming Address (four bytes): Start address for
programming
Multiple of the size specified in response to the programming
unit inquiry (i.e. H'00, H'01, H'00, H'00 : H'00010000)
24.2.1 Clock Division
Mode
972 Description amended
…In clock division mode, the CPU, bus masters, and on-chip
peripheral functions all operate on the operating clock (1/2,
1/4 ) specified by bits SCK2 to SCK0.
25.2 Register Bits 1004 Table amended
Register
Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module
FCCS
*
8
FLER——— ——— SCO FLASH