Datasheet

Section 6 Bus Controller (BSC)
Rev.7.00 Mar. 18, 2009 page 160 of 1136
REJ09B0109-0700
Bit Bit Name Initial Value R/W Description
4 EDDS 0 R/W EXDMAC Single Address Transfer Option
Selects whether full access is always performed or
burst access is enabled when EXDMAC single
address transfer is performed on the
DRAM/synchronous DRAM.
When the BE bit is cleared to 0 in DRAMCR,
disabling DRAM/synchronous DRAM burst access,
EXDMAC single address transfer is performed in
full access mode regardless of the setting of this
bit.
This bit has no effect on other bus master external
accesses or EXDMAC dual address transfers.
0: Full access is always executed
1: Burst access is enabled
3 — 0 R/W Reserved
This bit can be read from or written to. However,
the write value should always be 0.