Datasheet

Section 6 Bus Controller (BSC)
Rev.7.00 Mar. 18, 2009 page 166 of 1136
REJ09B0109-0700
T
p
RAS
SDWCD 0
CAS
DQMU, DQML
WE
CKE
Data bus
Address bus
SDRAMφ
φ
T
r
T
c1
T
cl
T
c2
PALL ACTV NOP WRIT NOP
T
p
T
r
T
c1
T
c2
Column address
Column address
Row address
Precharge-sel
Row address
Column address
High
RAS
SDWCD 1
CAS
DQMU, DQML
WE
CKE
Data bus
Address bus
PALL ACTV NOP WRIT
Row address
Precharge-sel
Row address
Column address
High
Figure 6.5 CAS Latency Control Cycle Disable Timing during Continuous Synchronous
DRAM Space Write Access (for CAS Latency 2)