Datasheet

Rev.7.00 Mar. 18, 2009 page xxiv of lxvi
REJ09B0109-0700
2.7.9 Effective Address Calculation ................................................................................ 66
2.8 Processing States.................................................................................................................. 68
2.9 Usage Note........................................................................................................................... 69
2.9.1 Note on Bit Manipulation Instructions.................................................................... 69
Section 3 MCU Operating Modes ....................................................................... 71
3.1 Operating Mode Selection.................................................................................................... 71
3.2 Register Descriptions...........................................................................................................72
3.2.1 Mode Control Register (MDCR) ............................................................................ 72
3.2.2 System Control Register (SYSCR)......................................................................... 72
3.3 Operating Mode Descriptions .............................................................................................. 75
3.3.1 Mode 1.................................................................................................................... 75
3.3.2 Mode 2.................................................................................................................... 75
3.3.3 Mode 3.................................................................................................................... 75
3.3.4 Mode 4.................................................................................................................... 75
3.3.5 Mode 5.................................................................................................................... 76
3.3.6 Mode 7.................................................................................................................... 76
3.3.7 Pin Functions .......................................................................................................... 77
3.4 Memory Map in Each Operating Mode ............................................................................... 78
Section 4 Exception Handling............................................................................. 93
4.1 Exception Handling Types and Priority............................................................................... 93
4.2 Exception Sources and Exception Vector Table.................................................................. 93
4.3 Reset..................................................................................................................................... 95
4.3.1 Reset Exception Handling....................................................................................... 95
4.3.2 Interrupts after Reset............................................................................................... 97
4.3.3 On-Chip Peripheral Functions after Reset Release................................................. 97
4.4 Trace Exception Handling.................................................................................................... 98
4.5 Interrupt Exception Handling............................................................................................... 98
4.6 Trap Instruction Exception Handling................................................................................... 99
4.7 Stack Status after Exception Handling............................................................................... 100
4.8 Usage Note......................................................................................................................... 101
Section 5 Interrupt Controller............................................................................ 103
5.1 Features.............................................................................................................................. 103
5.2 Input/Output Pins............................................................................................................... 105
5.3 Register Descriptions......................................................................................................... 105
5.3.1 Interrupt Control Register (INTCR)...................................................................... 106
5.3.2 Interrupt Priority Registers A to K (IPRA to IPRK)............................................. 106
5.3.3 IRQ Enable Register (IER) ................................................................................... 108
5.3.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL)...................................... 110