Datasheet

Section 6 Bus Controller (BSC)
Rev.7.00 Mar. 18, 2009 page 197 of 1136
REJ09B0109-0700
If a row address hold time or read access time is necessary, making a setting in bits RCD1 and
RCD0 in DRACCR allows from one to three T
rw
states, in which row address output is
maintained, to be inserted between the T
r
cycle, in which the RAS signal goes low, and the T
c1
cycle, in which the column address is output. Use the setting that gives the optimum row address
signal hold time relative to the falling edge of the RAS signal according to the DRAM connected
and the operating frequency of this LSI. Figure 6.24 shows an example of the timing when one T
rw
state is set.
T
p
RASn (CSn)
Read
Write
UCAS, LCAS
WE
(HWR)
OE (RD)
Data bus
WE (HWR)
OE (RD)
Data bus
Address bus
φ
T
r
T
rw
T
c1
T
c2
Row address Column address
High
High
Note: n = 2 to 5
Figure 6.24 Example of Timing with One Row Address Output Maintenance State
(RAST = 0, CAST = 0)