Datasheet

Rev.7.00 Mar. 18, 2009 page xxv of lxvi
REJ09B0109-0700
5.3.5 IRQ Status Register (ISR)..................................................................................... 116
5.3.6 IRQ Pin Select Register (ITSR)............................................................................ 117
5.3.7 Software Standby Release IRQ Enable Register (SSIER) .................................... 119
5.4 Interrupt Sources................................................................................................................ 120
5.4.1 External Interrupts ................................................................................................ 120
5.4.2 Internal Interrupts.................................................................................................. 121
5.5 Interrupt Exception Handling Vector Table....................................................................... 121
5.6 Interrupt Control Modes and Interrupt Operation.............................................................. 127
5.6.1 Interrupt Control Mode 0...................................................................................... 127
5.6.2 Interrupt Control Mode 2...................................................................................... 129
5.6.3 Interrupt Exception Handling Sequence ............................................................... 130
5.6.4 Interrupt Response Times ..................................................................................... 132
5.6.5 DTC and DMAC Activation by Interrupt............................................................. 133
5.7 Usage Notes ....................................................................................................................... 134
5.7.1 Conflict between Interrupt Generation and Disabling .......................................... 134
5.7.2 Instructions that Disable Interrupts....................................................................... 135
5.7.3 Times when Interrupts Are Disabled .................................................................... 135
5.7.4 Interrupts during Execution of EEPMOV Instruction........................................... 135
5.7.5 Change of IRQ Pin Select Register (ITSR) Setting .............................................. 135
5.7.6 IRQ Status Register (ISR)..................................................................................... 136
Section 6 Bus Controller (BSC).........................................................................137
6.1 Features.............................................................................................................................. 137
6.2 Input/Output Pins............................................................................................................... 139
6.3 Register Descriptions......................................................................................................... 142
6.3.1 Bus Width Control Register (ABWCR)................................................................ 143
6.3.2 Access State Control Register (ASTCR) .............................................................. 143
6.3.3 Wait Control Registers AH, AL, BH, and BL
(WTCRAH, WTCRAL, WTCRBH, and WTCRBL)............................................ 144
6.3.4 Read Strobe Timing Control Register (RDNCR) ................................................. 150
6.3.5 CS Assertion Period Control Registers H, L (CSACRH, CSACRL).................... 151
6.3.6 Area 0 Burst ROM Interface Control Register (BROMCRH)
Area 1 Burst ROM Interface Control Register (BROMCRL)............................... 153
6.3.7 Bus Control Register (BCR) ................................................................................. 154
6.3.8 DRAM Control Register (DRAMCR) .................................................................. 156
6.3.9 DRAM Access Control Register (DRACCR)....................................................... 164
6.3.10 Refresh Control Register (REFCR) ...................................................................... 167
6.3.11 Refresh Timer Counter (RTCNT)......................................................................... 170
6.3.12 Refresh Time Constant Register (RTCOR) .......................................................... 170
6.4 Bus Control........................................................................................................................ 171
6.4.1 Area Division........................................................................................................ 171