Datasheet

Rev.7.00 Mar. 18, 2009 page xxvi of lxvi
REJ09B0109-0700
6.4.2 Bus Specifications................................................................................................. 172
6.4.3 Memory Interfaces................................................................................................ 174
6.4.4 Chip Select Signals ............................................................................................... 175
6.5 Basic Bus Interface ............................................................................................................ 176
6.5.1 Data Size and Data Alignment.............................................................................. 176
6.5.2 Valid Strobes......................................................................................................... 178
6.5.3 Basic Timing......................................................................................................... 178
6.5.4 Wait Control ......................................................................................................... 187
6.5.5 Read Strobe (RD) Timing..................................................................................... 188
6.5.6 Extension of Chip Select (CS) Assertion Period................................................... 189
6.6 DRAM Interface ................................................................................................................ 191
6.6.1 Setting DRAM Space............................................................................................ 191
6.6.2 Address Multiplexing............................................................................................ 191
6.6.3 Data Bus................................................................................................................ 192
6.6.4 Pins Used for DRAM Interface............................................................................. 193
6.6.5 Basic Timing......................................................................................................... 194
6.6.6 Column Address Output Cycle Control................................................................ 195
6.6.7 Row Address Output State Control....................................................................... 196
6.6.8 Precharge State Control ........................................................................................ 198
6.6.9 Wait Control ......................................................................................................... 199
6.6.10 Byte Access Control ............................................................................................. 202
6.6.11 Burst Operation..................................................................................................... 203
6.6.12 Refresh Control..................................................................................................... 208
6.6.13 DMAC and EXDMAC Single Address Transfer Mode and DRAM Interface..... 213
6.7 Synchronous DRAM Interface........................................................................................... 216
6.7.1 Setting Continuous Synchronous DRAM Space................................................... 216
6.7.2 Address Multiplexing............................................................................................ 217
6.7.3 Data Bus................................................................................................................ 218
6.7.4 Pins Used for Synchronous DRAM Interface....................................................... 218
6.7.5 Synchronous DRAM Clock .................................................................................. 220
6.7.6 Basic Timing......................................................................................................... 220
6.7.7 CAS Latency Control............................................................................................ 222
6.7.8 Row Address Output State Control....................................................................... 224
6.7.9 Precharge State Count........................................................................................... 225
6.7.10 Bus Cycle Control in Write Cycle ........................................................................ 227
6.7.11 Byte Access Control ............................................................................................. 228
6.7.12 Burst Operation..................................................................................................... 231
6.7.13 Refresh Control..................................................................................................... 234
6.7.14 Mode Register Setting of Synchronous DRAM.................................................... 240
6.7.15 DMAC and EXDMAC Single Address Transfer Mode
and Synchronous DRAM Interface....................................................................... 241