Datasheet

Section 6 Bus Controller (BSC)
Rev.7.00 Mar. 18, 2009 page 221 of 1136
REJ09B0109-0700
T
p
SDRAMφ
RAS
Read
CAS
WE
CKE
PALL ACTV READ NOP
DQMU, DQML
Data bus
Address bus
φ
T
r
T
c1
T
c2
Row address Column address Column address
Precharge-sel
Row address
High
RAS
Write
CAS
WE
CKE
PALL ACTV NOP WRIT
DQMU, DQML
Data bus
High
Figure 6.44 Basic Access Timing of Synchronous DRAM (CAS Latency 1)