Datasheet

Section 6 Bus Controller (BSC)
Rev.7.00 Mar. 18, 2009 page 229 of 1136
REJ09B0109-0700
T
p
SDRAMφ
φ
RAS
CAS
WE
CKE
PALL ACTV READ NOP
DQMU
DQML
Lower data bus
Upper data bus
Address bus
T
r
T
c1
T
cl
T
c2
Row address Column address Column address
Precharge-sel
Row address
High
High
High impedance
Figure 6.50 DQMU and DQML Control Timing
(Lower Byte Read Access: CAS Latency 2)