Datasheet

Section 6 Bus Controller (BSC)
Rev.7.00 Mar. 18, 2009 page 252 of 1136
REJ09B0109-0700
Relationship between Chip Select (CS) Signal and Read (RD) Signal: Depending on the
system’s load conditions, the RD signal may lag behind the CS signal. An example is shown in
figure 6.68. In this case, with the setting for no idle cycle insertion (a), there may be a period of
overlap between the bus cycle A RD signal and the bus cycle B CS signal. Setting idle cycle
insertion, as in (b), however, will prevent any overlap between the RD and CS signals. In the
initial state after reset release, idle cycle insertion (b) is set.
T
1
A
ddress bus
φ
RD
Bus cycle A
T
2
T
3
T
1
T
2
Bus cycle B
Overlap period between CS (area B)
and RD may occur
(a) No idle cycle insertion
(ICIS1 = 0)
T
1
Address bus
Idle cycle
φ
Bus cycle A
T
2
T
3
T
i
T
1
Bus cycle B
(b) Idle cycle insertion
(ICIS1 = 1, initial value)
T
2
CS (area A)
CS (area B)
RD
CS (area A)
CS (area B)
Figure 6.68 Relationship between Chip Select (CS) and Read (RD)