Datasheet

Section 6 Bus Controller (BSC)
Rev.7.00 Mar. 18, 2009 page 256 of 1136
REJ09B0109-0700
6.73 and 6.74. In write access, DQMU and DQML are not in accordance with the settings of the
IDLC bit. The timing in this case is illustrated in figure 6.75.
T
p
Address bus External addressColumn address 1 Column address 2
External address
Row
address
Column
address
Idle cycle
Data bus
T
r
T
c1
T
cl
T
c2
T
3
T
c1
Continuous synchronous
DRAM space read External space read
Continuous synchronous
DRAM space read
T
2
T
i
T
1
RAS
CAS
WE
RD
HWR, LWR
CKE
High
High
PALL ACTV READ NOP
NOPREAD
DQMU, DQML
T
Cl
T
c2
Precharge-sel
φ
Row
address
Figure 6.73 Example of Idle Cycle Operation in RAS Down Mode
(Read in Different Area) (IDLC = 0, CAS Latency 2)