Datasheet

Section 6 Bus Controller (BSC)
Rev.7.00 Mar. 18, 2009 page 264 of 1136
REJ09B0109-0700
Table 6.11 Idle Cycles in Mixed Accesses to Normal Space and DRAM Continuous
Synchronous DRAM Space
Previous Access Next Access ICIS2 ICIS1 ICIS0 DRMI IDLC Idle cycle
⎯ 0 ⎯ ⎯ ⎯ Disabled
⎯ 1 ⎯ ⎯ 0 1 state inserted
Normal space read
(different area)
1 2 states inserted
⎯ 0 ⎯ ⎯ ⎯ Disabled
⎯ 1 ⎯ ⎯ 0 1 state inserted
DRAM
*
/continuous
synchronous DRAM
space read
1 2 states inserted
⎯ ⎯ 0 ⎯ ⎯ Disabled
⎯ ⎯ 1 ⎯ 0 1 state inserted
Normal space write
1 2 states inserted
⎯ ⎯ 0 ⎯ ⎯ Disabled
⎯ ⎯ 1 ⎯ 0 1 state inserted
Normal space read
DRAM
*
/continuous
synchronous DRAM
space write
1 2 states inserted
⎯ 0 ⎯ ⎯ ⎯ Disabled
⎯ 1 ⎯ 0 ⎯ Disabled
1 0 1 state inserted
Normal space read
1 2 states inserted
⎯ 0 ⎯ ⎯ ⎯ Disabled
⎯ 1 ⎯ 0 ⎯ Disabled
1 0 1 state inserted
DRAM
*
/continuous
synchronous DRAM
space read
1 2 states inserted
⎯ ⎯ 0 ⎯ ⎯ Disabled
⎯ ⎯ 1 0 ⎯ Disabled
1 0 1 state inserted
Normal space write
1 2 states inserted
⎯ ⎯ 0 ⎯ ⎯ Disabled
⎯ ⎯ 1 0 ⎯ Disabled
DRAM/continuous
synchronous DRAM
*
space read
DRAM
*
/continuous
synchronous DRAM
space write
1 0 1 state inserted
1 2 states inserted