Datasheet

Section 6 Bus Controller (BSC)
Rev.7.00 Mar. 18, 2009 page 267 of 1136
REJ09B0109-0700
T
p
Address bus
Idle cycle
Data bus
T
r
T
c1
T
cl
T
c2
Continuous synchronous
DRAM space write
Continuous synchronous
DRAM space read
T
c2
T
i
T
c1
RAS
CAS
WE
CKE
High
PALL ACTV READ NOP WRIT
DQMU, DQML
Precharge-sel
φ
External address
Column
address
Row
address
Column
address
Figure 6.82 Example of Timing for Idle Cycle Insertion in Case of Consecutive Read and
Write Accesses to Continuous Synchronous DRAM Space in RAS Down Mode
(SDWCD = 1, CAS Latency 2)