Datasheet

Section 7 DMA Controller (DMAC)
Rev.7.00 Mar. 18, 2009 page 291 of 1136
REJ09B0109-0700
Bit Bit Name Initial Value R/W Description
3
2
1
0
DTF3
DTF2
DTF1
DTF0
0
0
0
0
R/W
R/W
R/W
R/W
Data Transfer Factor 3 to 0
These bits select the data transfer factor (activation
source). The factors that can be specified differ
between normal mode and block transfer mode.
• Normal Mode
0000: Setting prohibited
0001: Setting prohibited
0010: Activated by DREQ pin falling edge input
(detected as a low level in the first transfer
after transfer is enabled)
0011: Activated by DREQ pin low-level input
010x: Setting prohibited
0110: Auto-request (cycle steal)
0111: Auto-request (burst)
1×××: Setting prohibited