Datasheet

Section 7 DMA Controller (DMAC)
Rev.7.00 Mar. 18, 2009 page 293 of 1136
REJ09B0109-0700
7.3.5 DMA Band Control Registers H and L (DMABCRH and DMABCRL)
DMABCR controls the operation of each DMAC channel. The bit functions in the DMACR
registers differ according to the transfer mode.
Short Address Mode:
• DMABCRH
Bit Bit Name Initial Value R/W Description
15 FAE1 0 R/W Full Address Enable 1
Specifies whether channel 1 is to be used in short
address mode or full address mode. In short
address mode, channels 1A and 1B can be used
as independent channels.
0: Short address mode
1: Full address mode
14 FAE0 0 R/W Full Address Enable 0
Specifies whether channel 0 is to be used in short
address mode or full address mode. In short
address mode, channels 0A and 0B can be used
as independent channels.
0: Short address mode
1: Full address mode
13 SAE1 0 R/W Single Address Enable 1
Specifies whether channel 1B is to be used for
transfer in dual address mode or single address
mode. This bit is invalid in full address mode.
0: Dual address mode
1: Single address mode