Datasheet

Section 7 DMA Controller (DMAC)

Rev.7.00 Mar. 18, 2009 page 318 of 1136

REJ09B0109-0700

In repeat mode, operation continues until the DTE bit in DMABCRL is cleared. To end the

transfer operation, therefore, the DTE bit should be cleared to 0. A transfer end interrupt request is

not sent to the CPU or DTC. By setting the DTE bit to 1 again after it has been cleared, the

operation can be restarted from the transfer after that terminated when the DTE bit was cleared.

Figure 7.7 illustrates operation in repeat mode.

ddress T

ddress B

Transfer

IOAR

1 byte or word transfer performed in

response to 1 transfer request

Legend:

Address T = L

Address B = L + (–1)

DTID

· (2

DTSZ

· (N – 1))

Where : L = Value set in MAR

N = Value set in ETCR

Figure 7.7 Operation in Repeat mode

Transfer requests (activation sources) consist of A/D converter conversion end interrupts, external

requests, SCI transmission complete and reception complete interrupts, and TPU channel 0 to 5

compare match/input capture A interrupts. External requests can only be specified for channel B.

Figure 7.8 shows an example of the setting procedure for repeat mode.