Datasheet

Rev.7.00 Mar. 18, 2009 page xxxvii of lxvi
REJ09B0109-0700
16.3.4 I
2
C Bus Interrupt Enable Register (ICIER)........................................................... 780
16.3.5 I
2
C Bus Status Register (ICSR) ............................................................................ 782
16.3.6 Slave address register (SAR) ................................................................................ 784
16.3.7 I
2
C Bus Transmit Data Register (ICDRT) ............................................................ 785
16.3.8 I
2
C Bus Receive Data Register (ICDRR).............................................................. 785
16.3.9 I
2
C Bus Shift Register (ICDRS)............................................................................ 785
16.4 Operation............................................................................................................................ 786
16.4.1 I
2
C Bus Format ..................................................................................................... 786
16.4.2 Master Transmit Operation................................................................................... 787
16.4.3 Master Receive Operation..................................................................................... 789
16.4.4 Slave Transmit Operation ..................................................................................... 791
16.4.5 Slave Receive Operation....................................................................................... 794
16.4.6 Noise Canceler...................................................................................................... 796
16.4.7 Example of Use..................................................................................................... 796
16.5 Interrupt Request................................................................................................................ 801
16.6 Bit Synchronous Circuit..................................................................................................... 802
16.7 Usage Notes ....................................................................................................................... 803
Section 17 A/D Converter..................................................................................805
17.1 Features.............................................................................................................................. 805
17.2 Input/Output Pins............................................................................................................... 807
17.3 Register Description........................................................................................................... 808
17.3.1 A/D Data Registers A to H (ADDRA to ADDRH) .............................................. 808
17.3.2 A/D Control/Status Register (ADCSR) ................................................................ 809
17.3.3 A/D Control Register (ADCR) ............................................................................. 811
17.4 Operation............................................................................................................................ 812
17.4.1 Single Mode.......................................................................................................... 812
17.4.2 Scan Mode ............................................................................................................ 812
17.4.3 Input Sampling and A/D Conversion Time........................................................... 813
17.4.4 External Trigger Input Timing.............................................................................. 815
17.5 Interrupt Source ................................................................................................................. 816
17.6 A/D Conversion Accuracy Definitions .............................................................................. 816
17.7 Usage Notes ....................................................................................................................... 818
17.7.1 Module Stop Mode Setting ................................................................................... 818
17.7.2 Permissible Signal Source Impedance .................................................................. 818
17.7.3 Influences on Absolute Precision.......................................................................... 819
17.7.4 Setting Range of Analog Power Supply and Other Pins....................................... 819
17.7.5 Notes on Board Design......................................................................................... 819
17.7.6 Notes on Noise Countermeasures ......................................................................... 819