Datasheet

Section 8 EXDMA Controller (EXDMAC)
Rev.7.00 Mar. 18, 2009 page 363 of 1136
REJ09B0109-0700
EDDAR can be read at all times by the CPU. When reading EDDAR for a channel on which
EXDMA transfer processing is in progress, a longword-size read must be executed. Do not write
to EDDAR for a channel on which EXDMA transfer is in progress. The initial values of EDDAR
are undefined.
8.3.3 EXDMA Transfer Count Register (EDTCR)
EDTCR specifies the number of transfers. The function differs according to the transfer mode. Do
not write to EDTCR for a channel on which EXDMA transfer is in progress.
Normal Transfer Mode:
Bit Bit Name Initial Value R/W Description
31
to
24
— All 0 — Reserved
These bits are always read as 0 and cannot be
modified.
23
to
0
All 0 R/W 24-Bit Transfer Counter
These bits specify the number of transfers. Setting
H'000001 specifies one transfer. Setting H'000000
means no specification for the number of transfers,
and the transfer counter function is halted. In this
case, there is no transfer end interrupt by the
transfer counter. Setting H'FFFFFF specifies the
maximum number of transfers, that is 16,777,215.
During EXDMA transfer, this counter shows the
remaining number of transfers.
This counter can be read at all times. When
reading EDTCR for a channel on which EXDMA
transfer processing is in progress, a longword-size
read must be executed.