Datasheet

Section 8 EXDMA Controller (EXDMAC)
Rev.7.00 Mar. 18, 2009 page 402 of 1136
REJ09B0109-0700
DMA write
HWR
ETEND
A
ddress bus
φ
Bus release Bus release Bus
releas
e
Last transfer cycle
EDACK
Bus release
DMA writeDMA write
LWR
Figure 8.25 Example of Single Address Mode (Word Write) Transfer
After one byte or word has been transferred in response to one transfer request, the bus is released.
While the bus is released, one or more CPU, DMAC, or DTC bus cycles are initiated.