Datasheet

Section 8 EXDMA Controller (EXDMAC)
Rev.7.00 Mar. 18, 2009 page 408 of 1136
REJ09B0109-0700
CPU cycle CPU cycle CPU cycle CPU cycle CPU cycle
External
space
External
space
External
space
External
space
External
space
1 bus cycle
Last transfer cycle
φ pin
EDACK
Bus cycle
CPU
operation
ETEND
EXDMA
single cycle
EXDMA
single cycle
EXDMA
single cycle
EXDMA
single cycle
EXDMA
single cycle
Figure 8.33 Auto Request/Burst Mode/Normal Transfer Mode
(CPU Cycles/Single Address Mode/BGUP = 1)
φ pin
Bus cycle
Original
channel
EDACK
Original
channel
ETEND
Other
channel
transfer
request
(EDREQ)
EXDMA single
transfer cycle
EXDMA single
transfer cycle
EXDMA single
transfer cycle
1 cycleLast transfer
cycle
Other channel EXDMA cycle
Bus release
Bus
release
Bus
release
Figure 8.34 Auto Request/Burst Mode/Normal Transfer Mode
(Contention with Another Channel/Single Address Mode)