Datasheet

Rev.7.00 Mar. 18, 2009 page xlvii of lxvi
REJ09B0109-0700
Figure 6.76 Example of Idle Cycle Operation after DRAM Access
(Consecutive Reads in Different Areas) (IDLC = 0, RAST = 0, CAST = 0).......... 259
Figure 6.77 Example of Idle Cycle Operation after DRAM Access
(Write after Read) (IDLC = 0, RAST = 0, CAST = 0)............................................ 260
Figure 6.78 Example of Idle Cycle Operation after DRAM Write Access
(IDLC = 0, ICIS1 = 0, RAST = 0, CAST = 0) ........................................................ 261
Figure 6.79 Example of Idle Cycle Operation after Continuous Synchronous DRAM Space
Read Access (Read between Different Area) (IDLC = 0, CAS Latency 2) ............ 262
Figure 6.80 Example of Idle Cycle Operation after Continuous Synchronous DRAM Space
Write Access (IDLC = 0, ICIS1 = 0, SDWCD = 1, CAS Latency 2)...................... 263
Figure 6.81 Example of Timing for Idle Cycle Insertion in Case of Consecutive Read and
Write Accesses to DRAM Space in RAS Down Mode........................................... 266
Figure 6.82 Example of Timing for Idle Cycle Insertion in Case of Consecutive Read
and Write Accesses to Continuous Synchronous DRAM Space in RAS Down
Mode (SDWCD = 1, CAS Latency 2)..................................................................... 267
Figure 6.83 Example of Timing when Write Data Buffer Function Is Used.............................. 269
Figure 6.84 Bus Released State Transition Timing .................................................................... 272
Figure 6.85 Bus Release State Transition Timing when Synchronous DRAM Interface........... 273
Section 7 DMA Controller (DMAC).................................................................279
Figure 7.1 Block Diagram of DMAC....................................................................................... 280
Figure 7.2 Areas for Register Re-Setting by DTC (Channel 0A)............................................. 305
Figure 7.3 Operation in Sequential Mode................................................................................. 313
Figure 7.4 Example of Sequential Mode Setting Procedure..................................................... 314
Figure 7.5 Operation in Idle Mode ........................................................................................... 315
Figure 7.6 Example of Idle Mode Setting Procedure................................................................ 316
Figure 7.7 Operation in Repeat mode....................................................................................... 318
Figure 7.8 Example of Repeat Mode Setting Procedure........................................................... 319
Figure 7.9 Operation in Single Address Mode (When Sequential Mode Is Specified) ............ 321
Figure 7.10 Example of Single Address Mode Setting Procedure
(When Sequential Mode Is Specified)..................................................................... 322
Figure 7.11 Operation in Normal Mode ..................................................................................... 324
Figure 7.12 Example of Normal Mode Setting Procedure.......................................................... 325
Figure 7.13 Operation in Block Transfer Mode (BLKDIR = 0)................................................. 327
Figure 7.14 Operation in Block Transfer Mode (BLKDIR = 1)................................................. 328
Figure 7.15 Operation Flow in Block Transfer Mode ................................................................ 329
Figure 7.16 Example of Block Transfer Mode Setting Procedure.............................................. 330
Figure 7.17 Example of DMA Transfer Bus Timing.................................................................. 331
Figure 7.18 Example of Short Address Mode Transfer.............................................................. 332
Figure 7.19 Example of Full Address Mode Transfer (Cycle Steal) .......................................... 333
Figure 7.20 Example of Full Address Mode Transfer (Burst Mode).......................................... 334