Datasheet

Section 9 Data Transfer Controller (DTC)
Rev.7.00 Mar. 18, 2009 page 430 of 1136
REJ09B0109-0700
9.2.5 DTC Transfer Count Register A (CRA)
CRA is a 16-bit register that designates the number of times data is to be transferred by the DTC.
In normal mode, the entire CRA functions as a 16-bit transfer counter (1 to 65,536). It is
decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000.
In repeat mode or block transfer mode, the CRA is divided into two parts: the upper 8 bits
(CRAH) and the lower 8 bits (CRAL). CRAH holds the number of transfers while CRAL
functions as an 8-bit transfer counter (1 to 256). CRAL is decremented by 1 every time data is
transferred, and the contents of CRAH are sent when the count reaches H'00.
9.2.6 DTC Transfer Count Register B (CRB)
CRB is a 16-bit register that designates the number of times data is to be transferred by the DTC in
block transfer mode. It functions as a 16-bit transfer counter (1 to 65,536) that is decremented by 1
every time data is transferred, and transfer ends when the count reaches H'0000. The CRB is not
available in normal and repeat modes.
9.2.7 DTC Enable Registers A to H (DTCERA to DTCERH)
DTCER which is comprised of seven registers, DTCERA to DTCERH, is a register that specifies
DTC activation interrupt sources. The correspondence between interrupt sources and DTCE bits is
shown in table 9.2. For DTCE bit setting, use bit manipulation instructions such as BSET and
BCLR for reading and writing. If all interrupts are masked, multiple activation sources can be set
at one time (only at the initial setting) by writing data after executing a dummy read on the
relevant register.
Bit Bit Name Initial Value R/W Description
7
6
5
4
3
2
1
0
DTCE7
DTCE6
DTCE5
DTCE4
DTCE3
DTCE2
DTCE1
DTCE0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
DTC Activation Enable
Setting this bit to 1 specifies a relevant interrupt source
to a DTC activation source.
[Clearing conditions]
• When the DISEL bit is 1 and the data transfer has
ended
• When the specified number of transfers have ended
These bits are not automatically cleared when the
DISEL bit is 0 and the specified number of transfers
have not ended
• When 0 is written to DTCE after reading DTCE = 1