Datasheet

Section 9 Data Transfer Controller (DTC)
Rev.7.00 Mar. 18, 2009 page 436 of 1136
REJ09B0109-0700
Origin of
Activation
Source
Activation
Source
Vector
Number
DTC Vector
Address
DTCE
*
Priority
TPU_3 TGI3A 56 H'0470 DTCED5 High
TGI3B 57 H'0472 DTCED4
TGI3C 58 H'0474 DTCED3
TGI3D 59 H'0476 DTCED2
TPU_4 TGI4A 64 H'0480 DTCED1
TGI4B 65 H'0482 DTCED0
TPU_5 TGI5A 68 H'0488 DTCEE7
TGI5B 69 H'048A DTCEE6
TMR_0 CMIA0 72 H'0490 DTCEE3
CMIB0 73 H'0492 DTCEE2
TMR_1 CMIA1 76 H'0498 DTCEE1
CMIB1 77 H'049A DTCEE0
DMAC DMTEND0A 80 H'04A0 DTCEF7
DMTEND0B 81 H'04A2 DTCEF6
DMTEND1A 82 H'04A4 DTCEF5
DMTEND1B 83 H'04A6 DTCEF4
SCI_0 RXI0 89 H'04B2 DTCEF3
TXI0 90 H'04B4 DTCEF2
SCI_1 RXI1 93 H'04BA DTCEF1
TXI1 94 H'04BC DTCEF0
SCI_2 RXI2 97 H'04C2 DTCEG7
TXI2 98 H'04C4 DTCEG6
SCI_3 RXI3 101 H'04CA DTCEF5
TXI3 102 H'04CC DTCEF4
SCI_4 RXI4 105 H'04D2 DTCEG3
TXI4 106 H'04D4 DTCEG2 Low
Note: * DTCE bits with no corresponding interrupt are reserved, and 0 should be written to.
When clearing the software standby state or all-module-clocks-stop mode with an
interrupt, write 0 to the corresponding DTCE bit.