Datasheet

Section 10 I/O Ports
Rev.7.00 Mar. 18, 2009 page 537 of 1136
REJ09B0109-0700
10.15.4 Port Function Control Register 0 (PFCR0)
PFCR0 performs I/O port control.
Bit Bit Name Initial Value R/W Description
7 CS7E 1 R/W
6 CS6E 1 R/W
5 CS5E 1 R/W
4 CS4E 1 R/W
3 CS3E 1 R/W
2 CS2E 1 R/W
1 CS1E 1 R/W
CS7 to CS0 Enable
These bits enable or disable the corresponding CSn
output.
0: Pin is designated as I/O port
1: Pin is designated as CSn output pin
(n = 7 to 0)
0 CS0E 1 R/W
10.15.5 Pin Functions
Port G pins also function as the pins for bus control signal I/Os. The correspondence between the
register specification and the pin functions is shown below.
Note: Only modes 1 and 2 are supported on ROM-less versions.
• PG6/BREQ
The pin function is switched as shown below according to the operating mode, bit EXPE, bit
BRLE, and bit PG6DDR.
Operating
mode
1, 2, 4 7
EXPE ⎯ 0 1
BRLE 0 1 ⎯ 0 1
PG6DDR 0 1 ⎯ 0 1 0 1 ⎯
Pin
function
PG6
input
PG6
output
BREQ
input
PG6 input PG6
output
PG6
input
PG6
output
BREQ input