Datasheet

Section 10 I/O Ports
Rev.7.00 Mar. 18, 2009 page 544 of 1136
REJ09B0109-0700
• PH1/CS5/RAS5/SDRAMφ
*
2
The pin function is switched as shown below according to the operating mode, DCTL pin, bit
EXPE, bit CS5E, bits RMTS2 to RMTS0, and bit PH1DDR.
DCTL
*
1
0 1
Operating
mode
1, 2, 4 7 ⎯
EXPE ⎯ 0 1 ⎯
Area 5 Normal space DRAM space ⎯ Normal space DRAM space ⎯
DCTL 0 1
CS5E 0 1 0 1 ⎯ 0 1 0 1 ⎯
PH1DDR 0 1 0 1 0 1 ⎯ 0 1 0 1 0 1 0 1 ⎯ ⎯
Pin function PH1
input
PH1
output
PH1
input
CS5
output
PH1
input
PH1
output
RAS5
output
PH1
input
PH1
output
PH1
input
PH1
output
PH1
input
CS5
output
PH1
input
PH1
output
RAS5
output
SDRAM
*
2
φ output
Notes: 1. When SDRAM interface is not used, input a low-level signal on the DCTL pin.
2. Not used in the H8S/2378 0.18μm F-ZTAT Group, H8S/2377, H8S/2375, and
H8S/2373.
• PH0/CS4/RAS4/WE
*
The pin function is switched as shown below according to the operating mode, bit EXPE, bit
CS4E, bits RMTS2 to RMTS0, and bit PH0DDR.
Operating
mode
1, 2, 4 7
EXPE ⎯ 0 1
Area 4 ⎯ Normal space DRAM
space
Syn-
chronous
DRAM
*
space
⎯ ⎯ Normal space DRAM
space
Syn-
chronous
DRAM
*
space
CS4E 0 1 ⎯ 0 1
PH0DDR 0 1 0 1 ⎯ ⎯ 0 1 0 1 0 1 ⎯ ⎯
Pin function PH0
input
PH0
output
PH0
input
CS4
output
RAS4
output
WE
*
output
PH0
input
PH0
output
PH0
input
PH0
output
PH0
input
CS4
output
RAS4
output
WE
*
output
Note: * Not used in the H8S/2378 0.18μm F-ZTAT Group, H8S/2377, H8S/2375, and
H8S/2373.