Datasheet

Section 11 16-Bit Timer Pulse Unit (TPU)
Rev.7.00 Mar. 18, 2009 page 622 of 1136
REJ09B0109-0700
11.10.6 Contention between TGR Write and Compare Match
If a compare match occurs in the T
2
state of a TGR write cycle, the TGR write takes precedence
and the compare match signal is disabled. A compare match also does not occur when the same
value as before is written.
Figure 11.47 shows the timing in this case.
Compare
match signal
Write signal
A
ddress
φ
TGR address
TCNT
TGR write cycle
T
1
T
2
N M
TGR write data
TGR
N N + 1
Disabled
Figure 11.47 Contention between TGR Write and Compare Match