Datasheet

Section 11 16-Bit Timer Pulse Unit (TPU)
Rev.7.00 Mar. 18, 2009 page 626 of 1136
REJ09B0109-0700
11.10.10 Contention between Buffer Register Write and Input Capture
If the input capture signal is generated in the T
2
state of a buffer register write cycle, the buffer
operation takes precedence and the write to the buffer register is not performed.
Figure 11.51 shows the timing in this case.
Input capture
signal
Write signal
A
ddress
φ
TCNT
Buffer register write cycle
T
1
T
2
N
TGR
N
M
M
Buffer
register
Buffer register
address
Figure 11.51 Contention between Buffer Register Write and Input Capture